An embodiment relates to a page buffer circuit of a nonvolatile memory device and a program operation and, more particularly, to a page buffer circuit, a nonvolatile memory device including the page buffer circuit, and a method of operating the nonvolatile memory device, wherein the program speeds of memory cells are classified into some groups and the program speeds of the memory cells are controlled on a group basis so that the memory cells have a threshold voltage distribution with a narrow width thereof.
A NAND flash memory device (i.e., a type of a nonvolatile memory device) includes a memory cell array, a row decoder, and a page buffer. The memory cell array includes word lines extending in rows, bit lines extending in columns, and cell strings corresponding to the respective bit lines.
The row decoder coupled to a string selection line, the word lines, and a common source line is placed on one side of the memory cell array. The page buffer coupled to the bit lines is placed on the other side of the memory cell array.
Recently, in order to further increase the degree of integration of flash memory devices, researches have been made on a multi-bit cell which is capable of storing plural data in one memory cell. This type of a memory cell is generally called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
Each of flash memory cells of a flash memory device includes a current path, formed between a source and a drain over a semiconductor substrate, and a floating gate and a control gate formed between insulating layers over the semiconductor substrate. Further, the program operation of a flash memory cell is generally performed by applying a high positive voltage to the control gate so that Fowler-Nordheim (F-N) tunneling is generated between the floating gate and the substrate in the state in which the source and drain regions of the memory cell and a semiconductor substrate (i.e., a bulk region) are grounded. In F-N tunneling, an electric field of a high voltage applied to the control gate causes electrons of the bulk region to be accumulated in the floating gate, and so the threshold voltage of the memory cell rises.
A nonvolatile memory device has higher reliability when the distribution of threshold voltages of a programmed memory cell has a narrower width thereof. Thus, it is important to narrow the distribution of threshold voltages when performing a program operation. One of the methods used to narrow the distribution of threshold voltages is a double verification method.
FIG. 1 is a diagram showing verification voltages when a double verification operation is performed in the distributions of threshold voltages.
Referring to FIG. 1, when memory cells included in a first threshold voltage distribution 110 (i.e., an erased cell state) are programmed, the threshold voltages of the memory cells shift to a second threshold voltage distribution 120.
Here, assuming that first cells C1 are memory cells having a fast program speed and second cells C2 are memory cells having a slow program speed, the distribution of threshold voltages of memory cells that should be programmed to have the second threshold voltage distribution 120 changes to a third threshold voltage distribution 130 because of the difference in the program speed for the same program voltage.
In order to control the program speeds of the memory cells, a double verification operation using a first verification voltage PV1 and a second verification voltage PV2 is carried out.
Although an actual program verification voltage is the second verification voltage PV2, the first memory cells C1 having a fast program speed are classified on the basis of the first verification voltage PV1.
The verification result of the first verification operation is stored in the latch of a page buffer of each bit line. Furthermore, a bit line voltage is changed according to a data state latched in the page buffer. A certain voltage (for example, a voltage higher than 0 V) is applied to a bit line that has passed the first verification operation, and 0 V is applied to a bit line that has not passed the first verification operation.
After the voltage is applied to the bit line as described above, a program voltage raised by a step voltage set according to an increment step program pulse (ISPP) method is applied to a corresponding word line, and a program operation is performed again.
When the voltage is applied to the bit line, the speed at which a memory cell that has passed the first verification operation is programmed can be reduced by controlling the degree of program for a program voltage. Accordingly, the width of a distribution of threshold voltages of memory cells can be narrowed by controlling the program speeds of memory cells that are rapidly programmed as compared with the program speeds of memory cells that are slowly programmed.
However, the double verification operation may have an extended program time because a verification operation must be performed twice whenever a program operation is performed and has limitations in narrowing the width of a distribution of threshold voltages because of the repeated performance of the verification operations.